Exploring Optimal Hardware Implementations with Hydra and OpenROAD
Measuring area and timing tradeoffs across hardware designs using open source tools.
Read postMeasuring area and timing tradeoffs across hardware designs using open source tools.
Read postHardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
Read postThe reproducible workflow behind the area and timing measurements from our previous experiment.
Read postMeasuring area and timing tradeoffs across hardware designs using open source tools.
Read postWith sphinx-svdomain, SystemVerilog source and docstrings become clear, linked documentation that is easy to browse and rebuild as the RTL changes.
Read postHardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
Read postAn open-source full-system workflow that connects PyTorch, a Linux driver, and Verilated RTL inside a Renode-simulated SoC before physical hardware is ready.
Read postCustom AI hardware creates value when repeated model operations can be moved into workload-specific datapaths for better latency, power, and integration. This post shows a small PyTorch-facing prototype that connects ordinary tensor code to that hardware path.
Read postA phase-by-phase RTL workflow that keeps modeling, generation, verification, synthesis, and timing open without closing the door to commercial backends.
Read postA lightweight verification workflow for building RTL with golden models, standard streaming interfaces, and composable blocks.
Read postMany “serial feedback” circuits look inherently sequential, but if their state update is linear over a finite field, we can raise the transition matrix to process many input symbols per clock.
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