Releasing sphinx-svdomain: Structured Documentation for SystemVerilog
Hardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
Hardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
A phase-by-phase RTL workflow that keeps modeling, generation, verification, synthesis, and timing open without closing the door to commercial backends.
With sphinx-svdomain, SystemVerilog source and docstrings become clear, linked documentation that is easy to browse and rebuild as the RTL changes.
Hardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
An open-source full-system workflow that connects PyTorch, a Linux driver, and Verilated RTL inside a Renode-simulated SoC before physical hardware is ready.
Custom AI hardware creates value when repeated model operations can be moved into workload-specific datapaths for better latency, power, and integration. This post shows a small PyTorch-facing prototype that connects ordinary tensor code to that hardware path.
A phase-by-phase RTL workflow that keeps modeling, generation, verification, synthesis, and timing open without closing the door to commercial backends.
A lightweight verification workflow for building RTL with golden models, standard streaming interfaces, and composable blocks.
Many “serial feedback” circuits look inherently sequential, but if their state update is linear over a finite field, we can raise the transition matrix to process many input symbols per clock.