A Practical Guide to Hardware Design Space Exploration
The reproducible workflow behind the area and timing measurements from our previous experiment.
HardMatrix
#open-source
6 posts
Exploring Optimal Hardware Implementations with Hydra and OpenROAD
Measuring area and timing tradeoffs across hardware designs using open source tools.
From Source to Documentation: Using sphinx-svdomain
With sphinx-svdomain, SystemVerilog source and docstrings become clear, linked documentation that is easy to browse and rebuild as the RTL changes.
Releasing sphinx-svdomain: Structured Documentation for SystemVerilog
Hardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
Building a Full-System Accelerator Prototype with Renode
An open-source full-system workflow that connects PyTorch, a Linux driver, and Verilated RTL inside a Renode-simulated SoC before physical hardware is ready.
Shipping Competitive RTL with Open Source Tools
A phase-by-phase RTL workflow that keeps modeling, generation, verification, synthesis, and timing open without closing the door to commercial backends.