A Practical Guide to Hardware Design Space Exploration
The reproducible workflow behind the area and timing measurements from our previous experiment.
HardMatrix
#rtl
7 posts
Exploring Optimal Hardware Implementations with Hydra and OpenROAD
Measuring area and timing tradeoffs across hardware designs using open source tools.
From Source to Documentation: Using sphinx-svdomain
With sphinx-svdomain, SystemVerilog source and docstrings become clear, linked documentation that is easy to browse and rebuild as the RTL changes.
Releasing sphinx-svdomain: Structured Documentation for SystemVerilog
Hardware APIs deserve searchable documentation with reliable links between declarations. We are releasing sphinx-svdomain to help close that gap.
Shipping Competitive RTL with Open Source Tools
A phase-by-phase RTL workflow that keeps modeling, generation, verification, synthesis, and timing open without closing the door to commercial backends.
Lightweight RTL Verification Flow with cocotb
A lightweight verification workflow for building RTL with golden models, standard streaming interfaces, and composable blocks.
Parallelizing Linear Feedback Systems with Matrices
Many “serial feedback” circuits look inherently sequential, but if their state update is linear over a finite field, we can raise the transition matrix to process many input symbols per clock.